IDT49C466

The IDT49C466/A 64-bit Flow-thruEDC is a high-speed error detection and correction unit that ensures data integrity in memoy stems.  The flow-thru architecture, with separate
system and memory data buses, is ideally suited for pipelined  memory systems.

Implementing a modified Hamming code, the IDT49C466/A corrects all single bit hard and soft errors, and detects all double bit errors.  The read/write FIFOs can store up to sixteen words.  FIFO full and empty flags indicate whether additional data can be written to or read from the EDC.

Diagnostic features include a check bit register,  syndrome registers, a four bit error counter which logs up to 15 errors,and an error data register which stores the complete error data
word.  Parity can be generated and checked on the system bus by the IDT49C466/A.