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Package Cooled:PLCC  D/C:06+  

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Part Number: IDT7007S

 

 

Package Cooled: PLCC

D/C: 06+

Description: The IDT7007 is a high-speed 32K x 8 Dual-Port Static RAM. The IDT7007 is designed to be used as a stan...


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IDT7007S General Description


The IDT7007 is a high-speed 32K x 8 Dual-Port Static RAM. The IDT7007 is designed to be used as a stand-alone 256K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.

This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very LOW standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 850mW of power. 

The IDT7007 is packaged in a 68-pin pin PGA, a 68-pin PLCC, and an 80-pin thin quad flatpack, TQFP. Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.

IDT7007S Maximum Ratings

Symbol Rating
Commercial
& Industrial
Military
Unit
VTERM(2) Terminal Voltage with Respect to GND
0.5 to +7.0
0.5 to +7.0
V
TBIAS Temperature Under Bias
55 to +125
55 to +135
TSTG Storage Temperature
55 to +120
65 to +150
IOUT DC Output Current
50
50
mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sec-tions of this specification is not implied. Exposure to absolute maxi-mum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to 20mA for the period of VTERM Vcc + 10%.

IDT7007S Features

` True Dual-Ported memory cells which allow simultaneous reads of the same memory location
` High-speed access
   - Military: 25/35/55ns (max.)
   - Industrial: 55ns (max.)
   - Commercial: 15/20/25/35/55ns (max.)
` Low-power operation
   - IDT7007S
       Active: 850mW (typ.)
       Standby: 5mW (typ.)
   - IDT7007L
       Active: 850mW (typ.)
       Standby: 1mW (typ.)
` IDT7007 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than
one device
` M/S = H for BUSY output flag on Master,M/S = L for BUSY input on Slave
` Interrupt Flag
` On-chip port arbitration logic
` Full on-chip hardware support of semaphore signaling between ports
` Fully asynchronous operation from either port
` TTL-compatible, single 5V (±10%) power supply
` Available in 68-pin PGA and PLCC and a 80-pin TQFP
` Industrial temperature range (-40°C to +85°C) is available for selected speeds

IDT7007S Connection Diagram

IDT7007S  Connection Diagram

IDT7007S datasheet

IDT7007S/L
PDF/DataSheet Download

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