IDT7017L

DescriptionThe IDT7017L provides two independent ports with separate control which is a high-speed 32K x 9 dual-port static RAM. The address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. Using the IDT MASTER/SLAVE Dual-Port RAM approach i...

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SeekIC No. : 004372003 Detail

IDT7017L: DescriptionThe IDT7017L provides two independent ports with separate control which is a high-speed 32K x 9 dual-port static RAM. The address, and I/O pins that permit independent, asynchronous acces...

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Part Number:
IDT7017L
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/28

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Product Details

Description



Description

The IDT7017L provides two independent ports with separate control which is a high-speed 32K x 9 dual-port static RAM. The address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 18-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (CE0 and CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDTs CMOS high performance technology, these devices typically operate on only 1W of power. The IDT7017 is packaged in a 100-pin Thin Quad Flatpack (TQFP). IDT7017L is designed to be used as a stand-alone 288K-bit Dual-Port RAM or as a combination MASTER/SLAVE dual-port RAM for 18-bit-or-more word systems.

The features of IDT7017L can be summarized as (1)true dual-ported memory cells which allow simultaneous reads of the same memory location; (2)high-speed access Commercial: 15/20ns (max.)/ industrial: 20ns (max.); (3)low-power operation IDT7017L, active: 1W (typ.), standby: 1mW (typ.); (4)dual chip enables allow for depth expansion without external logic; (5)IDT7017 easily expands data bus width to 18 bits or more using the Master/Slave select when cascading more than one device; (6)M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on slave; (7)interrupt flag; (8)on-chip port arbitration logic; (9)full on-chip hardware support of semaphore signaling between ports; (10)fully asynchronous operation from either port; (11)TTL-compatible, single 5V (±10%) power supply; (12)available in a 100-pin TQFP; (13)industrial temperature range (-40°C to +85°C) is available for selected speeds.

The absolute maximum ratings of IDT7017L are (1)VTERM(2: VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.) terminal voltage; (2)with respect to GND: -0.5 to +7.0 V; (3)TBIAS temperature under bias: -55 to +125°C; (4)TSTG storage temperature: -65 to +150°C; (5)IOUT DC output current: 50 mA. (Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.)




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