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IDT7035S/L

Features: True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access--Commercial: 15/20ns (max.) Low-power operation--IDT7035SActive: 800mW (typ.)Standby: 5mW (typ.)--IDT7035LActive: 800mW (typ.)Standby: 1mW (typ.)Separate upper-byte and lower-byte ...

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SeekIC No. : 004372020 Detail

IDT7035S/L: Features: True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access--Commercial: 15/20ns (max.) Low-power operation--IDT7035SActive: 800mW (typ.)Sta...

IDT7035S/L Data Sheet

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Part Number:
IDT7035S/L
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

True Dual-Ported memory cells which allow simultaneous reads of the same memory location
High-speed access
--Commercial: 15/20ns (max.)
Low-power operation
-- IDT7035S
Active: 800mW (typ.)
Standby: 5mW (typ.)
-- IDT7035L
Active: 800mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multiplexed bus compatibility
IDT7035 easily expands data bus width to 36 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for BUSY output flag on MasterM/S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signalingbetween ports
Fully asynchronous operation from either port
Battery backup operationó2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 100-pin Thin Quad Flatpack
Industrial temperature range (ñ40°C to +85°C) is available for selected speeds


Pinout

Connection Diagram
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.


Specifications

Symbol
Rating
Com'l & Ind'l
Unit
Military
VTERM
Terminal Voltage
with respect to GND
0.5 to +4.5
V
TSTG
Temperature Under
Bias
55 to +125
°C
TSTG
Storage
Temperature
-55 to +125
mA
IOUT
DC Output Current
50
mA
 

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20 mA for the period over VTERM > Vcc + 10%.




Description

The IDT7035S/L is a high-speed 8K x 18 Dual-Port Static RAM. The IDT7035S/L is designed to be used as a stand-alone 144K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit or more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory.

An automatic power down feature of the IDT7035S/L controlled by Chip Enable (CE) permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT7035 utilizes a 18-bit wide data path to alow for parity at the user's option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/ reception error checking. Fabricated using IDTís CMOS high-performance technology, these devices typically operate on only 800mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500µW from a 2V battery.




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