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IDT707288S/L

Features: 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture Four independent 16K x 16 banks 1 Megabit of memory on chip Fast asynchronous address-to-data access time: 15nsUser-controlled input pins included for bank selects Independent port controls with asynchronous address & data busses...

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SeekIC No. : 004372030 Detail

IDT707288S/L: Features: 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture Four independent 16K x 16 banks 1 Megabit of memory on chip Fast asynchronous address-to-data access time: 15nsUser-controlled input ...

IDT707288S/L Data Sheet

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Part Number:
IDT707288S/L
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

64K x 16 Bank-Switchable Dual-Ported SRAM Architecture
Four independent 16K x 16 banks
1 Megabit of memory on chip
Fast asynchronous address-to-data access time: 15ns
User-controlled input pins included for bank selects
Independent port controls with asynchronous address & data busses
Four 16-bit mailboxes available to each port for inter- processor communications; interrupt option
Interrupt flags with programmable masking
Dual Chip Enables allow for depth expansion without external logic
UB and LB are available for x8 or x16 bus matching
 TTL-compatible, single 5V (±10%) power supply
Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)


Pinout

Connection Diagram
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.


Specifications

Symbol
Rating
Com'l & Ind'l
Unit
Military
VTERM
Terminal Voltage
with respect to GND
0.5 to +4.5
V
 -0.5 to +7.0
TSTG
Temperature Under
Bias
55 to +125
°C
 -65 to +135
TSTG
Storage
Temperature
50 to +50
mA
 -65 to +150
IOUT
DC Output Current
50
mA
50

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.


Description

The IDT707288S/L is a high-speed 64K x 16 (1M bit) Bank-Switchable Dual-Ported SRAM organized into four independent 16K x 16 banks. The device has two independent ports with separate control, address, and I/O pins for each port, allowing each port to asynchronously access any 16K x 16 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via bank select pin inputs under the user's control. Mailboxes are provided to allow interprocessor communication. Interrupts are provided to indicate mailbox writes have occurred.

An automatic power down feature of the IDT707288S/L controlled by the chip enables (CE0 and CE1) permits the on-chip circuitry of each port to enter a very low standby power mode and allows fast depth expansion. The IDT707288S/L offers a maximum address-to-data access time as fast as 15ns, and is packaged in a 100-pin Thin Quad Flatpack (TQFP).




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