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IDT709149S

Features: Architecture based on Dual-Port SRAM cellsAllows full simultaneous access from both ports High-speed clock-to-data output times Commercial: 8/10/12ns (max.) Low-power operation IDT709149SActive: 1500mW (typ.)Standby: 75mW (typ.)4K X 9 bits Synchronous operation 4ns setup to clock, 1ns h...

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SeekIC No. : 004372042 Detail

IDT709149S: Features: Architecture based on Dual-Port SRAM cellsAllows full simultaneous access from both ports High-speed clock-to-data output times Commercial: 8/10/12ns (max.) Low-power operation IDT709149S...

IDT709149S Data Sheet

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Part Number:
IDT709149S
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

  Architecture based on Dual-Port SRAM cells
 Allows full simultaneous access from both ports
  High-speed clock-to-data output times
  Commercial: 8/10/12ns (max.)
  Low-power operation
  IDT709149S
Active: 1500mW (typ.)
Standby: 75mW (typ.)
 4K X 9 bits
  Synchronous operation
  4ns setup to clock, 1ns hold on all control, data, and address inputs
  Data input, address, and control registers
  Fast 8ns clock to data out
 13ns cycle time, 76MHz operation in pipeline mode
  Self-timed write allows for fast cycle times
 TTL-compatible, singles 5V (±10%) power supply
  Clock Enable feature
 Guaranteed data output hold times
 Industrial temperature range (ñ40°C to +85°C) is available for selected speeds.


Pinout

Connection Diagram
NOTES:
1. All VCC pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4, This package code is used to reference the package diagram.
5. This text does not indicate the orientaion of the actual part-marking.


Specifications

Symbol
Rating
Com'l & Ind'l
Unit
VTERM
Terminal Voltage
with respect to GND
-0.5 to +7.0
V
VTER(2)
Terminal Voltage
-0.5 to VCC
°C
TSTG
Temperature
Under Bias
-55 to +125
mA
IOUT
Storage
Temperature
50-55 to +125
mA
IOUT
DC Output Current
50
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. 3494 tbl 01


Description

The IDT709149S is a high-speed 4K x 9 bit synchronous Dual-Port SRAM. The memory array is based on Dual-Port memory cells to allow simultaneous access from both ports. Registers on control, data, and address inputs provide low set-up and hold times. The timing latitude provided by this approach will allow systems to be designed with very




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