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IDT70T3509M

Features: True Dual-Port memory cells which allow simultaneousaccess of the same memory location High-speed data access Commercial: 4.2ns (133MHz)(max.) Industrial: 4.2ns (133MHz)(max.) Selectable Pipelined or Flow-Through output mode Counter enable and repeat features Interrupt Flags Full synchr...

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SeekIC No. : 004372082 Detail

IDT70T3509M: Features: True Dual-Port memory cells which allow simultaneousaccess of the same memory location High-speed data access Commercial: 4.2ns (133MHz)(max.) Industrial: 4.2ns (133MHz)(max.) Selectable ...

IDT70T3509M Data Sheet

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Part Number:
IDT70T3509M
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
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Product Details

Description



Features:

True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
Commercial: 4.2ns (133MHz)(max.)
Industrial: 4.2ns (133MHz)(max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Interrupt Flags
Full synchronous operation on both ports
7.5ns cycle time, 133MHz operation (9.5Gbps bandwidth)
1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 133MHz
Fast 4.2ns clock to data out
NOTE:
1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
2. See Truth Table I for Functionality.
Data input, address, byte enable and control registers
Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Includes JTAG functionality
Available in a 256-pin Ball Grid Array (BGA)
Common BGA footprint provides design flexibility over
seven density generations (512K to 36M-bit)
Green parts available, see ordering information


Specifications

Symbol Rating Commercial
& Industrial		 Unit
VTERM
(VDD)		 VDD Terminal Voltage
with Respect to GND		 -0.5 to 3.6 V
VTERM(2)
(VDDQ)		 VDDQ Terminal Voltage
with Respect to GND		 -0.3 to VDDQ + 0.3 V
VTERM(2)
(INPUTS and I/O's)		 Input and I/O Terminal
Voltage with Respect to GND		 -0.3 to VDDQ + 0.3 V
TBIAS(3) Temperature Under Bias -55 to +125 oC
TSTG Storage Temperature -65 to +150 oC
TJN Junction Temperature +150 oC
IOUT(For VDDQ = 3.3V) DC Output Current 50 mA
IOUT(For VDDQ = 2.5V) DC Output Current 40 mA



Description

The IDT70T3509M is a high-speed 1024K x 36 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times.

The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70T3509M has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.

The IDT70T3509M can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.




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