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IDT70T631S

Features: On-chip port arbitration logic Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching compatibility Sleep Mode Inputs on both ports Supports JTAG features compliant to IEEE 1149.1 in BGA-208 and BGA-256 packages Single 2.5V (±100mV) pow...

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SeekIC No. : 004372090 Detail

IDT70T631S: Features: On-chip port arbitration logic Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching compatibility Sleep Mode Inputs on both ports Supp...

IDT70T631S Data Sheet

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Part Number:
IDT70T631S
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

On-chip port arbitration logic
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus matching compatibility
Sleep Mode Inputs on both ports
Supports JTAG features compliant to IEEE 1149.1 in BGA-208 and BGA-256 packages
Single 2.5V (±100mV) power supply for core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port
Available in a 256-ball Ball Grid Array, 144-pin Thin Quad Flatpack and 208-ball fine pitch Ball Grid Array
Industrial temperature range (40°C to +85°C) is available for selected speeds
True Dual-Port memory cells which allow simultaneous access of the same memory location
High-speed access
Commercial: 10/12/15ns (max.)
Industrial: 12ns (max.)
Dual chip enables allow for depth expansion without external logic
IDT70T633/1 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more than one device
M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
Full hardware support of semaphore signaling between ports on-chip


Pinout

Connection Diagram
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground.
4. A18X is a NC for IDT70T631.
5. Package body is approximately 20mm x 20mm x 1.4mm.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
8. Due to the restricted number of pins, JTAG is not supported in the DD-144 package.


Specifications

Symbol
Rating
Commercial
& Industrial
Unit
VTERM
(VDD)
VDD Terminal Voltage
with Respect to GND
-0.5 to 3.6
V
VTERM(2)
(VDDQ)
VDDQ Terminal Voltage
with Respect to GND
-0.3 to VDDQ + 0.3
V
VTERM(2)
(INPUTS and I/O's)
Input and I/O Terminal
Voltage with Respect to GND
-0.3 to VDDQ + 0.3
V
TBIAS(3)
 Temperature Under Bias
-55 to +125
°C
TSTG
Storage Temperature
-65 to +150
°C
TJN
Junction Temperature
+ 150
°C
IOUT(For VDDQ = 3.3V)
DC Output Current
50
mA
IOUT(For VDDQ = 2.5V)
DC Output Current
40
mA

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed VDDQ during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.




Description

The IDT70T631S is a high-speed 512/256K x 18 Asynchronous Dual-Port Static RAM. The IDT70T631S is designed to be used as a stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 36-bit-or-more word system.

Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.

The IDT70T631S can support an operating voltage of either 3.3V or 2.5V on one or both ports, controlled by the OPT pins. The power supply for the core of the device (VDD) remains at 2.5V.




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