IDT70V24S

Features:

 True Dual-Ported memory cells which allow simultaneous
    reads of the same memory location
 High-speed access
    Commercial: 15/20/25/35/55ns (max.)
    Industrial: 20/25/35/55ns (max.)
 Low-power operation
    IDT70V24S
        Active: 400mW (typ.)
        Standby: 3.3mW (typ.)
    IDT70V24L
        Active: 380mW (typ.)
        Standby: 660µW (typ.)
 Separate upper-byte and lower-byte control for multiplexed
    bus compatibility 
IDT70V24 easily expands data bus width to 32 bits or more
    using the Master/Slave select when cascading more than
    one device
 M/S = VIH for BUSYoutput flag on Master
    M/S = VIL for BUSY input on Slave
 BUSY and Interrupt Flag
 On-chip port arbitration logic
 Full on-chip hardware support of semaphore signaling
    between ports
 Fully asynchronous operation from either port
 LVTTL-compatible, single 3.3V (±0.3V) power supply
 Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP
 Industrial temperature range (-40°C to +85°C) is available
    for selected speeds


Pinout




Specifications

Symbol	Rating	Commercial & Industrial	Unit
VTERM(2)	Terminal Voltage with Respect to GND	-0.5 to +4.6	V
TBIAS	Temperature Under Bias	-55 to +125
TSTG	Storage Te mp e ra ture	-65 to +150
IOUT	DC Output Current	50	mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
 
2. VTERM must not exceed Vcc +0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to 20mA for the period over VTERM Vcc + 0.3V


Description

The IDT70V24S is a high-speed 4K x 16 Dual-Port Static RAM. The IDT70V24S is designed to be used as a stand-alone 64K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach n 32-bit or wider memory system applications results in full-speed, errorree operation without the need for additional discrete logic.

This IDT70V24S provides two independent ports with separate control,address, and I/O pins that permit independent, asyn-chronous access for reads or writes to any location in memory.  An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.

Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 400mW of power.

The IDT70V24S is packaged in a ceramic 84-pin PGA, an 84-Pin PLCC and a 100-pin Thin Quad Flatpack.