IDT71P71604

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V_DDQ must not exceed VDD during normal operation.

The IDT71P71604 Burst of two SRAMs are high-speed synchronous memories with a double-data-rate (DDR), bidirectional data port.

This scheme allows maximization of the bandwidth on the data bus by passing two data items per clock cycle. The address bus of the IDT71P71604 operates at single data rate speeds, allowing the user to fan out addresses and ease system design while maintaining maximum performance on data transfers.

The IDT71P71604 has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance.

All interfaces of the DDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface of the IDT71P71604 can be scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if necessary. The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. Clocking

The IDT71P71604 has two sets of input clocks, namely the K, K clocks and the C, C clocks. In addition, the DDRII has an output "echo" clock, CQ, CQ.