Features: 128K x 8 advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/GND) for reduced noise Equal access and cycle times Commercial: 10/12/15/20ns Industrial: 10/12/15/20ns One Chip Select plus one Output Enable pinInputs and outputs are LVTTL-compatibleSingle 3.3V sup...
IDT71V124SA: Features: 128K x 8 advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/GND) for reduced noise Equal access and cycle times Commercial: 10/12/15/20ns Industrial: 10/12/15/2...
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|
Symbol |
Rating |
Com'L. |
Unit |
|
VDD |
Supply Voltage Relative to GND |
-0.5 to +4.6 |
V |
|
VIN, VOUT |
Terminal Voltage Relative to GND |
-0.5 to VDD+0.5 |
V |
|
TA |
Commercial Operating Temperature |
0 to +70 |
°C |
|
Industrial Operating Temperature |
-40 to +85 | ||
|
TBIAS |
Temperature Under Bias |
-55 to +125 |
°C |
|
TSTG |
Storage Temperature |
-55 to +125 |
°C |
|
PT |
Power Dissipation |
1.25 |
W |
|
IOUT |
DC Output Current |
50 |
mA |
The IDT71V124SA is a 1,048,576-bit high-speed static RAM organized as 128K x 8. It is fabricated using IDT's high performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The JEDEC center power/GND pinout reduces noise generation and improves system performance.
The IDT71V124SA has an output enable pin which operates as fast as 5ns, with address access times as fast as 9ns available. All bidirectional inputs and outputs of the IDT71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.