IDT71V546

The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.  Thus it has been given the name ZBT TM,or Zero Bus Turn-around.

Address and control signals are applied to the SRAM during one clock cycle, and two cycles later its associated data cycle occurs, be itread or write.

The IDT71V546 contains data I/O, address and control signal regis-ters.  Output enable is the only asynchronous signal and can be used to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V546 to besuspended as long as necessary.  All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values.

There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired.  If any one of these three is not active when ADV/LD is low, no new memory operation can be initiated and any burst that was in progress is stopped. However, any pending data transfers (reads or writes) will be completed.  The data bus will tri-state two cycles after the chip is deselected or a write initiated.

The IDT71V546 has an on-chip burst counter.  In the burst mode, the IDT71V546 can provide four cycles of data for a single address presented to the SRAM.  The order of the burst sequence is defined by the LBOinput pin.  The  LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD=LOW)  or increment the internal burst counter (ADV/LD= HIGH).

The IDT71V546 SRAM utilizes IDT's high-performance, high-volume 3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) for high board density.