Features: • 64 x 8-bit organization (IDT72420)
• 256 x 8-bit organization (IDT72200)
• 512 x 8-bit organization (IDT72210)
• 1024 x 8-bit organization (IDT72220)
• 2048 x 8-bit organization (IDT72230)
• 4096 x 8-bit organization (IDT72240)
• 12 ns read/write cycle time (IDT72420/72200/72210)
• 15 ns read/write cycle time (IDT72220/72230/72240)
• Read and write clocks can be asynchronous orcoincidental
• Dual-Ported zero fall-through time architecture
• Empty and Full flags signal FIFO status
• Almost-empty and almost-full flags set to Empty+7 andFull-7, respectively
• Output enable puts output data bus in high-impedancestate
• Produced with advanced submicron CMOS technology
• Available in 28-pin 300 mil plastic DIP and 300 milceramic DIP
• For surface mount product please see the IDT72421/72201/72211/72221/72231/72241 data sheet
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40OC to +85OC) isavailable, tested to military electrical specifications
Pinout
Specifications
|
Symbol |
Rating |
Commercial |
Military |
Unit |
|
VTERM |
Terminal Voltagewith Respect toGND |
0.5 to + 7.0 |
0.5 to + 7.0 |
V |
|
TA |
Operating Temperature |
0 to + 70 |
55 to + 125 |
|
|
TBIAS |
Temperature Under Bias |
55 to + 125 |
65 to + 135 |
|
|
TSTG |
Storage Temperature |
55 to + 125 |
65 to + 135 |
|
|
IOUT |
DC Output
Current |
50 |
50 |
mA |
Description The IDT72240 SyncFIFO are very high-speed, low-power First-In, First-
Out (FIFO) memories with clocked read and write controls.The IDT72420/72200/72210/72220/72230/72240 have a 64,256, 512, 1024, 2048, and 4096 x 8-bit memory array, respec- tively. These FIFOs are applicable for a wide variety of data buffering needs, such as graphics, Local Area Networks (LANs), and interprocessor communication.
These FIFOs of the IDT72240 have 8-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and a write enable pin (WEN). Data is written into the Synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and a read enable pin (REN). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. An output enable pin (OE) is provided on the read port for three-state control of the output.
These Synchronous FIFOs of the IDT72240 have two end-point flags, Empty (EF) and Full (FF). Two partial flags, Almost-Empty (AE) and Almost-Full (AF), are provided for improved system control. The partial ( AE) flags are set to Empty+7 and Full-7 for AE and AF respectively.
The IDT72240 are fabri- cated using IDT's high-speed submicron CMOS technology. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B.
IDT72240 Data Sheet
