IDT72265

The IDT72255/72265 are monolithic, CMOS, high capacity,high speed, low power First-In, First-Out (FIFO) memorieswith clocked read and write controls. These FIFOs are applicablefor a wide variety of data buffering needs, such as opticaldisk controllers, local area networks (LANs), and inter-processorcommunication.

Both FIFOs have an 18-bit input port (Dn) and an 18-bitoutput port (Qn). The input port is controlled by a free-running clock (WCLK) and a data input enable pin (WEN). Data iswritten into the synchronous FIFO on every clock when WENis asserted. The output port is controlled by another clock pin(RCLK) and enable pin (REN). The read clock can be tied tothe write clock for single clock operation or the two clocks canrun asynchronously for dual clock operation. An output enablepin (OE) is provided on the read port for three-state control ofthe outputs.

The IDT72255/72265 have two modes of operation: In theIDT Standard Mode, the first word written to the FIFO isdeposited into the memory array. A read operation is requiredto access that word. In the First Word Fall Through Mode(FWFT), the first word written to an empty FIFO appearsautomatically on the outputs, no read operation required. Thestate of the FWFT/SI pin during Master Reset determines themode in use.