IDT72265LA

The IDT72255LA/72265LA are exceptionally deep, highspeed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls. These FIFOs offer numerous improvementsover previous SuperSync FIFOs, including the following:
• The limitation of the frequency of one clock input withrespect to the other has been removed. The FrequencySelect pin (FS) has been removed, thus it is no longernecessary to select which of the two clock inputs, RCLK orWCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixedand short.
• The first word data latency period, from the time the firstword is written to an empty FIFO to the time it can be read,
is now fixed and short. (The variable clock cycle countingdelay associated with the latency period found on previousSuperSync devices has been eliminated on this SuperSyncfamily.)
SuperSync FIFOs are particularly appropriate for network,video, telecommunications, data communications and other
applications that need to buffer large amounts of data.
The input port is controlled by a Write Clock (WCLK) inputand a Write Enable (WEN) input. Data is written into the FIFOon every rising edge of WCLK when WEN is asserted. Theoutput port is controlled by a Read Clock (RCLK) input andRead Enable (REN) input. Data is read from the FIFO on everyrising edge of RCLK when REN is asserted. AnOutput Enable(OE ) input is provided for three-state control of the outputs.