IDT723616

•Two independent FIFOs (64 X 36 storage capacity each) buffer data between bidirectional 36-bit port A and two unidirectional 18/9-bit ports (Port B transmits, Port C receives)
•Clock frequencies up to 67 MHz (10 ns access time) Free-running clock lines for each port: CLKA, CLKB and CLKC,may be asynchronous or coincident (simultaneous reading and writing of data is permitted)
•IDT Standard timing
•Empty flag functions: EFA (synchronized by CLKA) and EFB (synchronized by CLKB)
•Full flag functions: FFA (synchronized by CLKA) and FFC (synchronized by CLKC)
•Programmable Almost-Empty and Almost-Full flags; each has four default offsets (4, 8, 12 and 16)
•Bus sizing of 18-bits (word) and 9-bits (byte) for ports B and C
•Byte order swapping on ports B and C
•Passive parity checking on ports A and C
•Parity generation can be selected for ports A and B
•Master Reset clears data and configures FIFO
•Width can be easily expanded by adding FIFOs
•Auto power down minimizes power dissipation
•Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
•High performance sub-micron CMOS technology
•Industrial temperature range (40oC to +85oC) is available

The IDT723616 is a monolithic, high-speed, low-power, CMOS Triple Bus SyncFIFO (clocked) memory which supports clock frequencies up to 67 MHz and has read access times as fast as 10 ns. Two independent 64 x 36 dual-port SRAM FIFOs on board each chip buffer data between a bidirectional 36-bit bus (Port A) and two unidirectional 18-bit buses (Port B transmits data,Port C receives data.) FIFO data can be read out of ports B and written into port C using either 18-bit or 9-bit formats.

Reset (RST) initializes the read and write pointers to the first location of the memory array and selects one of four possible default flag offset settings: 4, 8,
12 or 16.

Each FIFO of the IDT723616 has flags to indicate empty and full conditions and two program-mable flags (Almost-Full and Almost-Empty) to indicate when a selected number of words is stored in memory. Data on Port B can be accessed in 18-bit and 9-bit formats. FIFO Data on Port C can be input in 18-bit and 9-bit formats. Byte-order swapping on ports B and C is possible with any bus size selection.Parity is checked passively on ports A and C and may be ignored if not desired.Parity generation can be selected for data read from ports A and B. Two or more devices can be used in parallel to create wider or deeper FIFO configurations.

This IDT723616 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous (free-running) port clock by enable signals.The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses controlled by a synchronous interface.