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MFG:IDT  Package Cooled:QFP  D/C:08+  

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Part Number: IDT72V201

 

MFG: IDT

Package Cooled: QFP

D/C: 08+

Description: The IDT72V201/72V211/72V221/72V231/72V241/72V251 SyncFIFOs™ are very high-speed, low-power First...


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IDT72V201 General Description


The IDT72V201/72V211/72V221/72V231/72V241/72V251 SyncFIFOs™ are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. The architecture, functional operation and pin assignments are identical to those of the IDT72201/72211/72221/72231/ 72241/72251, but operate at a power supply voltage (Vcc) between 3.0V and 3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-bit memory array, respectively. These FIFOs are applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication.

These FIFOs have 9-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and two Write Enable pins (WEN1, WEN2). Data is written into the Synchronous FIFO on every rising clock edge when the Write Enable pins are asserted. The output port is controlled by another clock pin (RCLK) and two Read Enable pins (REN1, REN2). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation. An Output Enable pin (OE) is provided on the read port for three-state control of the output.

The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF). Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are provided for improved system control. The programmable flags default to Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag offset loading is controlled by a simple state machine and is initiated by asserting the Load pin (LD).

These FIFOs are fabricated using IDT's high-speed submicron CMOS technology.

IDT72V201 Maximum Ratings

Symbol
Rating
Commercial &Industrial
Unit
VTERM(2)
Terminal Voltage with Respect to GND
0.5 to +5
V
TSTG
Storage Temperature
-55 to +125
oC
IOUT
DC Output Current
-55 to +50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the  specification i s  not  implied. Exposure  to  absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminal only.

IDT72V201 Features

` 256 x 9-bit organization IDT72V201
` 512 x 9-bit organization IDT72V211
` 1,024 x 9-bit organization IDT72V221
` 2,048 x 9-bit organization IDT72V231
` 4,096 x 9-bit organization IDT72V241
` 8,192 x 9-bit organization IDT72V251
` 10 ns read/write cycle time
` 5V input tolerant
` Read and Write clocks can be independent
` Dual-Ported zero fall-through time architecture
` Empty and Full Flags signal FIFO status
` Programmable Almost-Empty and Almost-Full flags can be set to any depth
` Programmable Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively
` Output Enable puts output data bus in high-impedance state
` Advanced submicron CMOS technology
` Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin plastic Thin Quad FlatPack (TQFP)
` Industrial temperature range (40°C to +85°C) is available

IDT72V201 Connection Diagram

IDT72V201  Connection DiagramIDT72V201  Connection Diagram

IDT72V201 datasheet

IDT72V201
PDF/DataSheet Download

  • Datasheet: IDT72V201
  • File Size: 118182 KB
  • Manufacturer: IDT [Integrated Device Technology]
  • Click here to Download

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