IDT72V2113

The IDT72V2103/72V2113 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x9/x18 data flow. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following:
• Flexible x9/x18 Bus-Matching on both read and write ports.
• The limitation of the frequency of one clock input with respect to the other has been removed. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK,is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync family.)
• Asynchronous/Synchronous translation on the read or write ports.
• High density offerings up to 4 Mbit.

Bus-Matching SuperSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.

Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW) and Output Width (OW) during the Master Reset cycle.

The input port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data present on the Dn data inputs is written into the FIFO on every rising edge of WCLK when WEN is asserted. During Asynchronous operation only the WR input is used to write data into the FIFO. Data is written on a rising edge of WR, the WEN input should be tied to its active state, (LOW).

The output port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. During Asynchronous operation only the RD input is used to read data from the FIFO. Data is read on a rising edge of RD, the REN input should be tied to its active state, LOW. When Asynchronous operation is selected on the output port the FIFO must be configured for Standard IDT mode, and the OE input used to provide three-state control of the outputs, Qn.

The frequencies of both the RCLK and the WCLK signals may vary from 0 to fMAX with complete independence. There are no restrictions on the frequency of the one clock input with respect to the other.

There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode.

In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines.

In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use.

FWFT/SI input during Master Reset determines the timing mode in use. For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required.

These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF functions are selected in IDT Standard mode. TheIR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode.

PAE and PAF can be programmed independently to switch at any point in memory. Programmable offsets determine the flag switching threshold and can be loaded by two methods: parallel or serial. Eight default offset settings are also provided, so that PAE can be set to switch at a predefined number of locations from the empty boundary and thePAF threshold can also be set at similar predefined values from the full boundary. The default offset values are set during Master Reset by the state of the FSEL0, FSEL1, and LD pins.

For serial programming, SEN together with LD on each rising edge of WCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WEN together with LD on each rising edge of WCLK, are used to load the offset registers via Dn. REN together with LD on each rising edge of RCLK can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading has been selected.

During Master Reset (MRS) the following events occur: the read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode.

The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programming method, and default or programmed offset settings existing before Partial Reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable.

It is also possible to select the timing mode of the PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modes can be set to be either asynchronous or synchronous for the PAE and PAF flags.
 
If asynchronous PAE/PAF configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOWto-
HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.

If synchronous PAE/PAF configuration is selected , the PAE is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. The mode desired is configured during master reset by the state of the Programmable Flag Mode (PFM) pin.

The Retransmit function allows data to be reread from the FIFO more than once. A LOW on the RT input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. A zero-latency retransmit timing mode can be selected using the Retransmit timing Mode pin (RM). During Master Reset, a LOW on RM will select zerolatency retransmit. A HIGH on RM during Master Reset will select normal latency.

If zero-latency retransmit operation is selected the first data word to be retransmitted will be placed on the output register with respect to the same RCLK edge that initiated the retransmit based on RT being LOW.

Refer to Figure 11 and 12 for Retransmit Timing with normal latency. Refer to Figure 13 and 14 for Retransmit Timing with zero-latency.

A Big-Endian/Little-Endian data word format is provided. This function is useful when data is written into the FIFO in long word format (x18) and read out of the FIFO in small word (x9) format. If Big-Endian mode is selected, then the most significant byte (word) of the long word written into the FIFO will be read out of the FIFO first, followed by the least significant byte. If Little-Endian format is selected, then the least significant byte of the long word written into the FIFO will be read out first, followed by the most significant byte. The mode desired is configured during master reset by the state of the Big-Endian (BE) pin.

select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If Interspersed Parity mode is selected, then the FIFO will assume that the parity bit is located in bit position D8 during the parallel programming of the flag offsets. If Non-Interspersed Parity mode is selected, then D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during Master Reset by the state of the IP input pin. This mode is relevant only when the input width is set to x18 mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not effect the data written to and read from the FIFO.

A JTAG test port is provided, here the FIFO has fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.

If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state.

The IDT72V2103/72V2113 are fabricated using IDT's high speed submicron CMOS technology.