IDT72V255LA

The IDT72V255LA/72V265LA are functionally compatible versions of theIDT72255/72265 designed to run off a 3.3V supply for very low powerconsumption. The IDT72V255LA/72V265LA are exceptionally deep, highspeed, CMOS First-In-First-Out (FIFO) memories with clocked read andwrite controls. These FIFOs offer numerous improvements over previousSuperSync FIFOs, including the following:
· The limitation of the frequency of one clock input with respect to the otherhas been removed. The Frequency Select pin (FS) has been removed,thus it is no longer necessary to select which of the two clock inputs, RCLKor WCLK, is running at the higher frequency.
· The period required by the retransmit operation is now fixed and short.
· The first word data latency period, from the time the first word is written to
an empty FIFO to the time it can be read, is now fixed and short. (The variableclock cycle counting delay associated with the latency period found onprevious SuperSync devices has been eliminated on this SuperSyncfamily.)
SuperSync FIFOs are particularly appropriate for networking, video,telecommunications, data communications and other applications that need tobuffer large amounts of data.
The input port is controlled by a Write Clock (WCLK) input and a Write Enable(WEN) input. Data is written into the FIFO on every rising edge of WCLK whenWEN is asserted. The output port is controlled by a Read Clock (RCLK) inputand Read Enable (REN) input. Data is read from the FIFO on every risingedge of RCLK when REN is asserted. An Output Enable (OE) input is providedfor three-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals may vary from 0to fMAX with complete independence. There are no restrictions on thefrequency of one clock input with respect to the other.