IDT72V36103

The IDT72V3683/72V3693/72V36103 are designed to run off a 3.3V supply for exceptionally low power consumption.  These devices are monolithic, high-speed, low-power, CMOS unidirectional Synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5 ns.  The 16,384/32,768/65,536 x 36 dual-port SRAM FIFO buffersdata from Port A to Port B.  FIFO data on Port B can output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian configurations.

These devices are  synchronous (clocked) FIFOs, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals.  The clocks for each port are independent of one another and can be asynchronous or