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Part Number: IDT72V3613

 

 

 

 

Description: The IDT72V3613 is a pin and functionally compatible version of the IDT723613, designed to run off a 3....


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IDT72V3613 General Description


The IDT72V3613 is a pin and functionally compatible version of the IDT723613, designed to run off a 3.3V supply for exceptionally low-power consumption. This device is a monolithic, high-speed, low-power, CMOS synchronous (clocked) FIFO memory which supports clock frequencies up to 83 MHz and has read-access times as fast as 8 ns. The 64 x 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO operates in IDT Standard mode and has flags to indicate empty and full conditions, and two programmable flags, Almost-Full (AF) and Almost-Empty (AE), to indicate when a selected number of words is stored in memory. FIFO data on port B can be output in 36- bit, 18-bit, and 9-bit formats with a choice of Big- or Little-Endian configurations.

IDT72V3613 Maximum Ratings

Symbol Rating Commercial Unit
VCC Supply Voltage Range 0.5 to +4.6 V
VI(2) Input Voltage Range 0.5 to VCC+0.5 V
VO(2) Output Voltage Range 0.5 to VCC+0.5 V
IIK Input Clamp Current (VI < 0 or VI > VCC) ±20 mA
IOK Output Clamp Current (VO = < 0 or VO > VCC) ±50 mA
IOUT Continuous Output Current (VO = 0 to VCC) ±50 mA
ICC Continuous Current Through VCC or GND ±500 mA
TSTG Storage Temperature Range 65 to 150 °C


NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

IDT72V3613 Features

• 64 x 36 storage capacity FIFO buffering data from Port A to Port B
• Supports clock frequencies up to 83MHz
• Fast access times of 8ns
• Free-running CLKA and CLKB may be asynchronous or
  coincident (permits simultaneous reading and writing of data on
  a single clock edge)
• Mailbox bypass registers in each direction
• Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),
  and 9 bits (byte)
• Selection of Big- or Little-Endian format for word and byte bus sizes
• Three modes of byte-order swapping on Port B
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
FF , AF flags synchronized by CLKA
EF , AE flags synchronized by CLKB
• Passive parity checking on each Port
• Parity Generation can be selected for each Port
• Available in 132-pin plastic quad flat package (PQF), or space
  saving 120-pin thin quad flat package (TQFP)
• Pin and functionally compatible version of the 5V operating IDT723613
• Industrial temperature range (40°C to +85°C) is available

IDT72V3613 Connection Diagram

IDT72V3613  Connection Diagram

IDT72V3613 datasheet

IDT72V3613
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