IDT72V3626

The IDT72V3626/72V3636/72V3646 are pin and functionally compatible versions of the IDT723626/723636/723646, designed to run off a 3.3V supply for exceptionally low-power consumption.  These devices are a monolithic,high-speed, low-power, CMOS Triple Bus synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5ns.  Two independent 256/512/1,024 x 36 dual port SRAMFIFOs on board each chip buffer data between a bidirectional 36-bit bus (PortA) and two unidirectional 18-bit buses (Port B transmits data, Port C receives data.)  FIFO data can be read out of Port B and written into Port C using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations.

These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for