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Part Number: IDT72V3631

 

 

 

 

Description: The IDT72V3631/72V3641/72V3651 are pin and functionally compatible versons of the IDT723631/7236...


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IDT72V3631 General Description


The IDT72V3631/72V3641/72V3651 are pin and functionally compatible  versons of the IDT723631/723641/723651, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are monolithic high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10ns. The 512/1,024/2,048 x 36 dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO operates in First Word Fall Through mode and has flags to indicate empty and full conditions and conditions and two programmable flags (Almost-Full and Almost-Empty) to

IDT72V3631 Maximum Ratings

Symbol Rating Commercial Unit
VCC Supply Voltage Range 0.5 to +4.6 V
VI(2) Input Voltage Range 0.5 to VCC+0.5 V
VO(2) Output Voltage Range 0.5 to VCC+0.5 V
IIK Input Clamp Current (VI < 0 or VI > VCC) ±20 mA
IOK Output Clamp Current (VO = < 0 or VO > VCC) ±50 mA
IOUT Continuous Output Current (VO = 0 to VCC) ±50 mA
ICC Continuous Current Through VCC or GND ±400 mA
TSTG Storage Temperature Range 65 to 150 °C


NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
3. Control Inputs: maximum VI = 5.0V.

IDT72V3631 Features

` Storage capacity: IDT72V3631 - 512 x 36
  IDT72V3641 - 1,024 x 36
  IDT72V3651 - 2,048 x 36
` Supports clock frequencies up to 67 MHz
` Fast access times of 10ns
` Free-running CLKA and CLKB can be asynchronous or coincident
  (permits simultaneous reading and writing of data on a
  single clock edge)
` Clocked FIFO buffering data from Port A to Port B
` Synchronous read retransmit capability
` Mailbox register in each direction
` Programmable Almost-Full and Almost-Empty flags
` Microprocessor interface control logic
` Input Ready (IR) and Almost-Full (AF) flags synchronized by CLKA
` Output Ready (OR) and Almost-Empty (AE) flags synchronized by CLKB
` Available in 132-pin plastic quad flat package (PQFP) or spacesaving
  120-pin thin quad flat package (TQFP)
` Pin and functionally compatible versions of the 5V operating
  IDT723631/723641/723651
` Easily expandable in width and depth
` Industrial temperature range (40°C to +85°C) is available

IDT72V3631 Connection Diagram

IDT72V3631  Connection Diagram

IDT72V3631 datasheet

IDT72V3631
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