IDT72V3634

The IDT72V3624/72V3634/72V3644 are pin and functionally compatible versions of the IDT723624/723634/723644, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are monolithic, highspeed, low-power, CMOS bidirectional synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can be input and output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little- Endian configurations.

These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or