Features: • Choose among the following memory organizations:
IDT72V7230 512 x 72
IDT72V7240 1,024 x 72
IDT72V7250 2,048 x 72
IDT72V7260 4,096 x 72
IDT72V7270 8,192 x 72
IDT72V7280 16,384 x 72
IDT72V7290 32,768 x 72
IDT72V72100 65,536 x 72
• 100 MHz operation (10 ns read/write cycle time)
• User selectable input and output port bus-sizing
- x72 in to x72 out
- x72 in to x36 out
- x72 in to x18 out
- x36 in to x72 out
- x18 in to x72 out
• Big-Endian/Little-Endian user selectable word representation
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for Almost-Empty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing simultaneously)
• Asynchronous operation of Output Enable, OE
• Read Chip Select ( RCS ) on Read Side
• Available in a 256-pin Fine Pitch Ball Grid Array package (PBGA)
• Features JTAG (Boundary Scan)
• High-performance submicron CMOS technology
• Industrial temperature range (40°C to +85°C) is availableSpecifications
| Symbol |
Rating |
Commercial |
Unit |
| VTERM |
Terminal Voltage
with respect to GND |
0.5 to +4.5 |
V |
TSTG
|
Storage
Temperature |
55 to +125 |
|
| IOUT |
DC Output Current |
50 to +50 |
mA |
DescriptionThe IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/72V7290/72V72100 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x72/x36/x18 data flow. These FIFOs offer several key user benefits:
• Flexible x72/x36/x18 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short.
• High density offerings up to 4 Mbit
Bus-Matching Sync FIFOs are particularly appropriate for network, video,telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either a 72-bit, 36-bit or a 18-bit width as determined by the state of external control pins Input Width (IW), Output Width (OW), and Bus-atching (BM) pin during the Master Reset cycle.
The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the IFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. An Output Enable (OE) input is provided for three-state control of the outputs.
A Read Chip Select (RCS) input is also provided for synchronous enable and disable of the read port control input, REN. The RCS input is synchronized to the read clock, and also provides three-state control of the Qn outputs. When RCS is disable, REN will be disabled internally and data outputs will be in High-Impedance state.
The frequencies of both the RCLK and the WCLK signals may vary from 0 to fMAX with complete independence. There are no restrictions on the frequency of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall hrough (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge,will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use.For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use,irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point in memory. Programmable offsets determine the flag switching threshold and can be loaded by two methods: parallel or serial. Eight default offset settings are alsoprovided, so that PAE can be set to switch at a predefined number of locations from the empty boundary and the PAF threshold can also be set at similar predefined values from the full boundary. The default offset values are set during Master Reset by the state of the FSEL0, FSEL1, and LD pins.
For serial programming, SEN together with LD on each rising edge of SCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WEN together with LD on each rising edge of WCLK, are used to load the offset registers via Dn. REN together with LD on each rising edge of RCLK can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading has been selected.
IDT72V7240 Data Sheet
