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Part Number: IDT72V73263

 

 

 

 

Description: The IDT72V73263 has a non-blocking switch capacity of 16,384 x 16,384 channels at 32.768Mb/s. With 64 ...


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IDT72V73263 General Description


The IDT72V73263 has a non-blocking switch capacity of 16,384 x 16,384 channels at 32.768Mb/s. With 64 inputs and 64 outputs, programmable per stream control, and a variety of operating modes the IDT72V73263 is designed for the TDM time slot interchange function in either voice or data applications.

Some of the main features of the IDT72V73263 are LOW power 3.3 Volt operation, automatic ST-BUS® /GCI sensing, memory block programming, simple microprocessor interface , JTAG Test Access Port (TAP) and per stream programmable input offset delay, variable or constant throughput modes, output enable and processor mode, BER testing, bypass mode, and advanced block programming.

IDT72V73263 Maximum Ratings

Symbol Parameter Min. Max. Unit
VCC Supply Voltage -0.5 +4.0 V
Vi Voltage on Digital Inputs GND -0.3 VCC +0.3 V
IO Current at Digital Outputs -50 50 mA
TS Storage Temperature -55 +125 °C
PD Package Power Dissapation   2 W

NOTE:
1. Exceeding these values may cause permanent damage. Functional operation under
these conditions is not implied.

IDT72V73263 Features

• Up to 64 serial input and output streams
• Maximum 16,384 x 16,384 channel non-blocking switching
• Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s,
  16.384Mb/s or 32.768Mb/s
• Rate matching capability: rate selectable on both RX and TX
in eight groups of 8 streams
• Optional Output Enable Indication Pins for external driver tri-state control
• Per-channel Variable Delay Mode for low-latency applications
• Per-channel Constant Delay Mode for frame integrity applications
• Enhanced Block programming capabilities
• TX/RX Internal Bypass
• Automatic identification of ST-BUS and GCI serial streams
• Per-stream frame delay offset programming
• Per-channel High-Impedance output control
• Per-channel processor mode to allow microprocessor writes to TX streams
• Bit Error Rate Testing (BERT) for testing
• Direct microprocessor access to all internal memories
• Selectable Synchronous and Asynchronous Microprocessor
  bus timing modes
• IEEE-1149.1 (JTAG) Test Port
• Available in 208-pin (28mm x 28mm) Plastic Quad Flatpack (PQFP)
  and 208-pin (17mm x 17mm) Plastic Ball Grid Array (PBGA)
• Operating Temperature Range -40°C to +85°C

IDT72V73263 Connection Diagram

IDT72V73263  Connection Diagram

IDT72V73263 datasheet

IDT72V73263
PDF/DataSheet Download

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