IDT72V825

The IDT72V825 are dual 18-bit-wide synchronous (clocked) First-in, First-out (FIFO) memories designed to run off a 3.3V supply for exceptionally low power consumption. One dual DT72V805/72V815/72V825/72V835/72V845 device is functionally equivalent to two DT72V205/72V215/72V225/72V235/72V245 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins. These devices are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These FIFOs are applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication.
Each of the two FIFOs contained in these devices of the IDT72V825 has an 18-bit input and output port. Each input port is controlled by a free-running clock (WCLK), and an input enable pin (WEN). Data is read into the synchronous FIFO on every clock when WEN is asserted. The output port of each FIFO bank is controlled by another clock pin (RCLK) and another enable pin (REN). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation. An Output Enable pin (OE) is provided on the read port of each FIFO for three-state control of the output.

The synchronous FIFOs of the IDT72V825 have two fixed flags, Empty Flag/Output Ready (EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the programmable flags is controlled by a simple state machine, and is initiated by asserting the Load pin (LD). A Half-Full flag (HF) is available for each FIFO that is implemented as a single device.

There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard Mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines.

In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word.

These devices of the IDT72V825 are depth expandable using a Daisy-Chain technique or First Word Fall Through (FWFT) mode. The XI and XO pins are used to expand the FIFOs. In depth expansion configuration, FL is grounded on the first device and set to HIGH for all other devices in the Daisy Chain. The IDT72V805/72V815/72V825/72V835/72V845 are fabricated using IDT's high-speed submicron CMOS technology.