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Part Number: IDT73720A
Description: The IDT73720/A Bus Exchanger is a high speed 16-bit bus exchange device intended for inter-bus communication ininte...
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IDT73720A
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DataSheet
General Description
IDT73720A General Description
The IDT73720/A Bus Exchanger is a high speed 16-bit bus exchange device intended for inter-bus communication in
interleaved memory systems and high performance multiplexed address and data busses.
The Bus Exchanger is responsible for interfacing between the CPU A/D bus (CPU address/data bus) and multiple
memory data busses.
The 73720/A uses a three bus architecture (X, Y, Z), with control signals suitable for simple transfer between the CPU
bus (X) and either memory bus (Y or Z). The Bus Exchanger features independent read and write latches for each memory bus, thus supporting a variety of memory strategies. All three ports support byte enable to independently enable upper and lower bytes.
IDT73720A Maximum Ratings
| Symbol | Rating | Com'l | Mil | Unit |
| VTERM | Terminal Voltage with Respect to GND |
0.5 to +7.0 | 0.5 to+7.0 | V |
| TA | Operating | 0 to +70 | 55 to +125 | °C |
| TBIAS | Temperature Under Bias | 55 to +125 | 65 to +135 | °C |
| TSTG | Storage Temperature |
55 to +125 | 65 to +125 | °C |
| PT | Power Dissipation | 1.0 | 1.0 | W |
| IOUT | DC Output Current | 50 | 50 | mA |
IDT73720A Features
• High-speed 16-bit bus exchange for interbus communication in the following environments:
- Multi-way interleaving memory
- Multiplexed address and data busses
• Direct interface to R3051 family RISChipSet
- R3051 family of integrated RISController CPUs
- R3721 DRAM controller
• Data path for read and write operations
• Low noise 12mA TTL level outputs
• Bidirectional 3-bus architecture: X, Y, Z
- One CPU bus: X
- Two (interleaved or banked) memory busses:Y & Z
- Each bus can be independently latched
• Byte control on all three busses
• Source terminated outputs for low noise and undershoot control
• 68-pin PLCC and 80-pin PQFP package
• High-performance CMOS technology.
- Multi-way interleaving memory
- Multiplexed address and data busses
• Direct interface to R3051 family RISChipSet
- R3051 family of integrated RISController CPUs
- R3721 DRAM controller
• Data path for read and write operations
• Low noise 12mA TTL level outputs
• Bidirectional 3-bus architecture: X, Y, Z
- One CPU bus: X
- Two (interleaved or banked) memory busses:Y & Z
- Each bus can be independently latched
• Byte control on all three busses
• Source terminated outputs for low noise and undershoot control
• 68-pin PLCC and 80-pin PQFP package
• High-performance CMOS technology.
IDT73720A
PDF/DataSheet Download
- Datasheet: IDT73720A
- File Size: 76607 KB
- Manufacturer: IDT [Integrated Device Technology]
- Click here to Download
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