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IDT74ALVC125

Features: 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 3.3V ± 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range VCC = 2.5V ± 0.2V CMOS power levels (0.4W typ. static) Rail-to-Rail output swing for increased noise...

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SeekIC No. : 004372716 Detail

IDT74ALVC125: Features: 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 3.3V ± 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range ...

IDT74ALVC125 Data Sheet

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Part Number:
IDT74ALVC125
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

 0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015;
   > 200V using machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SOIC, SSOP and TSSOP packages

Drive Features for ALVC125:
 High Output Drivers: ±24mA
Suitable for heavy loads


Application

• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems


Pinout

Connection Diagram


Specifications

Symbol Description Max. Unit
VTERM(2) Terminal Voltage with Respect to GND 0.5 to + 4.6 V
VTERM(3) Terminal Voltage with Respect to GND 0.5 to VCC + 0.5 V
TSTG Storage Temperature 65 to + 150 °C
IOUT DC Output Current 50 to + 50 mA
IIK Continuous Clamp Current, VI < 0 or VI > VCC
 ± 50 mA
IOK Continuous Clamp Current, VO < 0 50 mA
ICC
ISS		 Continuous Current through each
VCC or GND		 ±100 mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.




Description

This quadruple bus buffer gate of the IDT74ALVC125 is built using advanced dual metal CMOS technology. The ALVC125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)input is high.

The IDT74ALVC125 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.




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