IDT74ALVC162525

This 18-bit registered bus transceiver is built using advanced dual metal CMOS technology. Data flow in each direction is controlled by output-enable (OEAB and OEBA) and clock-enable (CLKENAB and CLKENBA) inputs. For the A-to-B data flow, the data flows through a single register.

The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL) input. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKEN inputs are low.

The A-to-B data transfer is synchronized to the CLKAB input, and B-to-A data transfer is synchronized with the CLK1BA and CLK2BA inputs. The ALVCH162525 has series resistors in the device output structure of the "B" port which will significantly reduce line noise when used with light loads.

This driver has been designed to drive ±12mA at the designated threshold levels. The "A" port has a ±24mA driver. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The ALVCH162525 has "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.