IDT74ALVCH16901

    This 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. The ALVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can  operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction.
    The ALVCH16901 features independent clock (CLKAB  or CLKAB ), latch-enable (LEAB or LEBA), and dual 9-bit clock enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable ( SEL ) and parity-select(ODD/EVEN ) inputs and separate error-signal (ERRA  and ERRB) outputs for checking parity. The direction of data flow is controlled by OEAB and OEBA. When SEL is low, the parity functions are enabled.  When SEL is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver.
    The ALVCH16901 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
    The ALVCH16901 has "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance.  This prevents floating inputs and eliminates the need for pull-up/down resistors.