IDT74ALVCH16903

This 12-bit universal bus driver is built using advanced dual metal CMOS technology. This device has dual outputs and can operate as a buffer or an edge-triggered register. In both modes, parity is checked on APAR, which arrives one cycle after the data to which it applies. The YERR output, which is produced one cycle after APAR, is open drain. MODE selects one of the two data paths. When MODE is low, the device operates as an edge-triggered register.

On the positive transition of the clock (CLK) input and when the clock-enable (CLKEN) input is low, data setup at the A inputs is stored in the internal registers. On the positive transition of CLK and when CLKEN is high, only data setup at the 9A-12A inputs is stored in their internal registers. When MODE is high, the device operates as a buffer and data at the A inputs passes directly to the outputs.

The 11A/YERREN serves a dual purpose; it acts as a normal data bit and also enables YERR data to be clocked into the YERR output register. When used as a single device, parity output enable (PAROE) must be tied high; when parity input/output (PARI/O) is low, even parity is selected and when PARI/O is high, odd parity is selected. When used in pairs and PAROE is low, the parity sum is output on PARI/O for cascading to the second ALVCH16903.

When used in pairs and PAROE is high, PARI/O accepts a partial parity sum from the first ALVCH16903. A buffered output-enable (OE) input can be used to place the 24 outputs and YERR in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

The ALVCH16903 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.