IDT74ALVCH32501

This 36-bit universal bus transceiver is built using advanced dual metal CMOS technology. The ALVCH32501 combines D-type latches and Dtype flip-flops to allow data flow in transparent latched and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs.

For A-to-B data flow, the device operates in transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a HIGH or low logic level. If LEAB is low, the A bus data is stored in the latch/ flip-flop on the low-to-high transition of CLKAB. OEAB performs the output enable function on the B port.

Data flow from B port to A port is similar but requires using OEBA, LEBA and CLKBA. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. This ALVCH32501 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

The ALVCH32501 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.