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Description: The FCT163601/A 18-bit registered transceiver is built using advanced dual metal CMOS technology. Thes...


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IDT74FCT163601 General Description


The FCT163601/A 18-bit registered transceiver is built using advanced dual metal CMOS technology. These 18-bit universal bus transceivers combine D-type latches and Dtype flip-flops to allow data flow in transparent, latched and clocked modes.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock(CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low.When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.Data flow for B to A is similar to that of A to B but uses OEBA,LEBA, CLKBA and CLKENBA.The FCT163601 has series current limiting resistors. These offer low ground bounce, minimal undershoot, and controlled output fall times-reducing the need for external series terminating resistors.

IDT74FCT163601 Maximum Ratings

ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max. Unit
VTERM(2)

Terminal Voltage with Respect to GND 0.5 to +4.6 V
VTERM(3)
Terminal Voltage with
Respect to GND
0.5 to +7.0 V
VTERM(4)
Terminal Voltage with
Respect to GND
0.5 to
VCC + 0.5

V
TSTG Storage Temperature 65 to +150 °C
IOUT DC Output Current 60 to +60 mA
                                                                                                        3251 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.

IDT74FCT163601 Features

• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015;
          > 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP and 15.7 mil pitch TVSOP
• Extended commercial range of -40°C to +85°C
• VCC = 3.3V ±0.3V, Normal Range or VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4mW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V components

IDT74FCT163601 Connection Diagram

IDT74FCT163601  Connection DiagramIDT74FCT163601  Connection Diagram

IDT74FCT163601 datasheet

IDT74FCT163601
PDF/DataSheet Download

  • Datasheet: IDT74FCT163601
  • File Size: 106991 KB
  • Manufacturer: IDT [Integrated Device Technology]
  • Click here to Download

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