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IDT74FCT3573A

Features: • 0.5 MICRON CMOS Technology• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)• VCC = 3.3V ±0.3V, Normal Range• VCC = 2.7V to 3.6V, Extended Range• CMOS power levels (0.4W typ. static)• Rail-to-Rail output s...

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SeekIC No. : 004373032 Detail

IDT74FCT3573A: Features: • 0.5 MICRON CMOS Technology• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)• VCC = 3.3V ±0.3V, Normal Range• VCC = 2...

IDT74FCT3573A Data Sheet

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Part Number:
IDT74FCT3573A
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ±0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in QSOP, SOIC, and TSSOP packages


Pinout

Connection Diagram


Specifications

Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
0.5 to +4.6
V
VTERM(3)
Terminal Voltage with Respect to GND
0.5 to +7
V
VTERM(4)
Terminal Voltage with Respect to GND
0.5 to VCC+0.5
V
TSTG
Storage Temperature
65 to +150
°C

IOUT
DC Output Current
60 to +60
mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Outputs and I/O terminals.




Description

The IDT74FCT3573A are octal transparent latches built using an advanced dual metal CMOS technology.

These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is high. When LE is low, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is low. When OE is high, the bus output is in the high-impedance state.




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