IDT74GTLP816

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operationalsections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Unused inputs must be held HIGH or LOW.

The GTLP816 is a GTLP to TTL (1:6) and TTL to GTLP (1:2) clock driver with inverting outputs. The clock driver IDT74GTLP816 provides a high-speed interface between cards operating at TTL logic levels and back-planes operating at GTLP logic levels. GTLP provides reduced output swing (<1V), reduced input threshold levels, and output edge-rate control to minimize signal setting times. The GTLP816 is a derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3 and incorporates internal edge-rate control, which is process, voltage, and temperature (PVT) compensated.

GTLP IDT74GTLP816 output low voltage is typically less than 0.5V. The output high is 1.5V, and the receiver threshold is 1V.

The GTLP816 is available in Industrial Temperature Range (-40°C to +85°C). See Ordering Information for details.