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Part Number: IDT74GTLP816
Description: The GTLP816 is a GTLP to TTL (1:6) and TTL to GTLP (1:2) clock driver with inverting outputs. The cloc...
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IDT74GTLP816
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DataSheet
General Description
IDT74GTLP816 General Description
The GTLP816 is a GTLP to TTL (1:6) and TTL to GTLP (1:2) clock driver with inverting outputs. The clock driver provides a high-speed interface between cards operating at TTL logic levels and back-planes operating at GTLP logic levels. GTLP provides reduced output swing (<1V), reduced input threshold levels, and output edge-rate control to minimize signal setting times. The GTLP816 is a derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3 and incorporates internal edge-rate control, which is process, voltage, and temperature (PVT) compensated.
GTLP output low voltage is typically less than 0.5V. The output high is 1.5V, and the receiver threshold is 1V.
The GTLP816 is available in Industrial Temperature Range (-40°C to +85°C). See Ordering Information for details.
IDT74GTLP816 Maximum Ratings
|
Symbol |
Rating |
Max. |
Unit | |
|
VCC |
Supply Voltage |
0.5 to +7 |
V | |
|
VCCQ | ||||
|
VI |
DC Input Voltage |
0.5 to +7 |
V | |
|
VO |
DC Output Voltage, 3-State |
3-State |
0.5 to +7 |
V |
|
Active |
0.5 to VCC + 0.5 | |||
|
IOL |
DC Output Sink Current into A-port |
64 |
mA | |
|
IOH |
DC Output Source Current from A-port |
-64 |
mA | |
|
IOL |
DC Output Sink Current into B-port(in the LOW state) |
80 |
mA | |
|
IIK |
DC Input Diode Current VI < 0V |
50 |
mA | |
|
IOK |
DC Output Diode Current
|
VO < 0V |
50 |
mA |
|
IOK |
VO > VCC |
+50 |
mA | |
|
TSTG |
Storage Temperature |
65 to +150 |
°C | |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operationalsections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Unused inputs must be held HIGH or LOW.
IDT74GTLP816 Features
• Interface between GTLP and TTL logic levels
• GTLP to TTL 1:6 fanout
• TTL to GTLP 1:2 fanout
• Edge Rate Control Circuit reduces output noise on GTLP port
• VREF pin provides reference voltage for receiver threshold
• CMOS technology for low power dissipation
• Special PVT Compensation circuitry to provide consistent performance over variations of process, supply voltage,
and temperature
• 5V tolerant inputs and outputs on TTL ports
• TTL-compatible Driver and Control inputs
• High Output source/sink ±24mA on TTL ports
• High Output sink +34mA on GTLP ports
• Open drain on GTLP to support wired-or connection
• Available in TSSOP package
• GTLP to TTL 1:6 fanout
• TTL to GTLP 1:2 fanout
• Edge Rate Control Circuit reduces output noise on GTLP port
• VREF pin provides reference voltage for receiver threshold
• CMOS technology for low power dissipation
• Special PVT Compensation circuitry to provide consistent performance over variations of process, supply voltage,
and temperature
• 5V tolerant inputs and outputs on TTL ports
• TTL-compatible Driver and Control inputs
• High Output source/sink ±24mA on TTL ports
• High Output sink +34mA on GTLP ports
• Open drain on GTLP to support wired-or connection
• Available in TSSOP package
IDT74GTLP816 Connection Diagram
IDT74GTLP816
PDF/DataSheet Download
- Datasheet: IDT74GTLP816
- File Size: 65774 KB
- Manufacturer: IDT
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