IDT74LVC112A

This dual negative-edge-triggered J-K flip-flop is built using advanced dual metal CMOS technology. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negativegoing edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the holdtime interval, data at the J and K inputs can be changed without affecting the levels at the outputs. The LVC112A can perform as a toggle flip-flop by tying J and K high.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVC112A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.