Features: • 0.5 MICRON CMOS Technology• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)• VCC = 3.3V ± 0.3V, Normal Range• VCC = 2.7V to 3.6V, Extended Range• CMOS power levels (0.4 W typ. static)• Rail-to-Rail output...
IDT74LVC112A: Features: • 0.5 MICRON CMOS Technology• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)• VCC = 3.3V ± 0.3V, Normal Range• VCC = ...
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Symbol |
Description |
Max |
Unit |
VTERM |
Terminal Voltage with Respect to GND |
0.5 to +6.5 |
V |
TSTG |
Storage Temperature |
65 to +150 |
°C |
IOUT |
DC Output Current |
50 to +50 |
mA |
IIK IOK |
Continuous Clamp Current, VI < 0 or VO < 0 |
50 |
mA |
ICC ISS |
Continuous Current through each VCC or GND |
±100 |
mA |
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
This dual negative-edge-triggered J-K flip-flop is built using advanced dual metal CMOS technology. A low level at the preset (PRE) or clear (CLR)IDT74LVC112A inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negativegoing edge of the clock pulse. Clock triggering of IDT74LVC112A occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the holdtime interval, data at the J and K inputs can be changed without affecting the levels at the outputs. The LVC112A can perform as a toggle flip-flop by tying J and K high.
Inputs of IDT74LVC112A can be driven from either 3.3V or 5V devices. This feature allows the use of IDT74LVC112A as a translator in a mixed 3.3V/5V supply system. The LVC112A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.