IDT74LVC16373A

Features: Typical tSK(0) (Output Skew) < 250psESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packagesExtended commercial range of -40to +85VCC = 3.3V ±0.3V, Normal RangeVCC = 2.7V to 3.6V...

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SeekIC No. : 004373150 Detail

IDT74LVC16373A: Features: Typical tSK(0) (Output Skew) < 250psESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch ...

floor Price/Ceiling Price

Part Number:
IDT74LVC16373A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/2

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Product Details

Description



Features:

Typical tSK(0) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packages
Extended commercial range of -40to +85
VCC = 3.3V ±0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4W typ. static)
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion




Application

•5V and 3.3V mixed voltage systems
•Data communication and telecommunication systems




Pinout

  Connection Diagram


Specifications

Symbol Description Max. Unit
VTER(2) Terminal Voltage with
Respect to GND
0.5 to +6.5 V
VTER(3) Terminal Voltage with
Respect to GND
0.5 to +6.5 V
TSTG Storage Temperature 65 to +150
IOUT DC Output Current 50 to +50 mA
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
50 mA
ICC
ISS
Continuous Current through
each VCC or GND
±100 mA



Description

The LVC16373A 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high-speed, low-power latch is ideal for temporary storage of data. The LVC16373A can be used for implementing memory address latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls are organized to operate each device as two 8-
bit latches or one 16-bit latch. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin.

All pins of the LVC16373A can be driven from either 3.3V or 5V devices. This feature of IDT74LVC16373A allows the use of this device as a translator in a mixed 3.3V/ 5V supply system.

The LVC16373A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.




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