IDT74LVC16601A

The LVC16601A 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. This 18-bit universal bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs.

For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/ flip-flop on the LOW-to-HIGH transition of CLKAB. Output enable OEAB is active low. WhenOEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA.

All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system.

The LVC16601A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.