Features: • Typical tSK(o) (Output Skew) < 250ps• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)• VCC = 3.3V ± 0.3V, Normal Range• VCC = 2.7V to 3.6V, Extended Range• CMOS power levels (0.4 W typ. static)• All in...
IDT74LVC16652A: Features: • Typical tSK(o) (Output Skew) < 250ps• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)• VCC = 3.3V ± 0.3V, Normal Range&...
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|
Symbol |
Description |
Max |
Unit |
|
VTERM |
Terminal Voltage with Respect to GND |
0.5 to +6.5 |
V |
|
TSTG |
Storage Temperature |
65 to +150 |
°C |
|
IOUT |
DC Output Current |
50 to +50 |
mA |
|
IIK IOK |
Continuous Clamp Current, VI < 0 or VO < 0 |
50 |
mA |
|
ICC ISS |
Continuous Current through each VCC or GND |
±100 |
mA |
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
The IDT74LVC16652A 16-bit registered transceiver is built using advanced dual metal CMOS technology. This high-speed, low power device is organized as two independent 8-bit bus transceivers with 3-state D-type registers. For example, the OEAB and OEBA signals control the transceiver functions.
The SAB and the SBA control pins of the IDT74LVC16652A are provided to select either real time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real time data. A Low input level selects real-time data and a High level selects stored data.
Data on the A or B data bus, or both, can be stored in the internal D-flipflops by the Low-to-High transitions at the appropriate clock pins (CLKAB or CLKBA), regardless of the select or enable control pins. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin.
The IDT74LVC16652A is ideally suited for driving high capacitance loads and low-impedance backplanes.
All pins can be driven from either a 3.3V or 5V device. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system.