IDT74LVC652A

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The LVC652A octal bus transceiver/register is built using advanced dual metal CMOS technology. IDT74LVC652A consists of a bus transceiver circuit, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and a high input selects stored data. Data on the A or B data bus, or both, is stored in the internal D-type flipflops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA)inputs, regardless of the select- or enable-control pins. When the SAB and SBA are in the real-time transfer mode, IDT74LVC652A is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. The LVC652A has been designed with a ±24mA output driver. IDT74LVC652A is capable of driving a moderate to heavy load while maintaining speed performance.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of IDT74LVC652A as a translator in a mixed 3.3V/5V system environment.