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Part Number: IDT74LVCH162823A
Description: The LVCH162823A 18-bit bus interface register is built using advanced dual metal CMOS technology. This...
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IDT74LVCH162823A
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General Description
IDT74LVCH162823A General Description
The LVCH162823A 18-bit bus interface register is built using advanced dual metal CMOS technology. This high-speed, low-power register with clock enable (CLKEN) and clear (CLR) controls is ideal for parity bus interfacing in high-performance synchronous systems. The control inputs are organized to operate the device as two 9-bit registers or one 18-bit register. Flow-through organization of signal pins simplifies layput. All inputs are designed with hysteresis for improved noise margin.
All pins of the LVCH162823A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVCH162823A has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been developed to drive ±12mA at the designated threshold levels.
The LVCH162823A has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
IDT74LVCH162823A Maximum Ratings
|
Symbol |
Description |
Max |
Unit |
|
VTERM |
Terminal Voltage with Respect to GND |
0.5 to +6.5 |
V |
|
TSTG |
Storage Temperature |
65 to +150 |
°C |
|
IOUT |
DC Output Current |
50 to +50 |
mA |
|
IIK IOK |
Continuous Clamp Current, VI < 0 or VO < 0 |
50 |
mA |
|
ICC |
Continuous Current through each VCC or GND |
±100 |
mA |
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
IDT74LVCH162823A Features
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4 W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
• Balanced Output Drivers: ±12mA
• Low switching noise
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4 W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
• Balanced Output Drivers: ±12mA
• Low switching noise
IDT74LVCH162823A Typical Application
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
• Data communication and telecommunication systems
IDT74LVCH162823A Connection Diagram
IDT74LVCH162823A
PDF/DataSheet Download
- Datasheet: IDT74LVCH162823A
- File Size: 76091 KB
- Manufacturer: IDT
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