IDT74SSTU32864A

Features: * 1:1 and 1:2 registered buffer* 1.8V Operation* SSTL_18 style clock and data inputs* Differential CLK input* Control inputs compatible with LVCMOS levels* Flow-through architecture for optimum PCB design* Latch-up performance exceeds 100mA* ESD >2000V per MIL-STD-883, Method 3015; &g...

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SeekIC No. : 004373241 Detail

IDT74SSTU32864A: Features: * 1:1 and 1:2 registered buffer* 1.8V Operation* SSTL_18 style clock and data inputs* Differential CLK input* Control inputs compatible with LVCMOS levels* Flow-through architecture for op...

floor Price/Ceiling Price

Part Number:
IDT74SSTU32864A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/27

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Product Details

Description



Features:

* 1:1 and 1:2 registered buffer
* 1.8V Operation
* SSTL_18 style clock and data inputs
* Differential CLK input
* Control inputs compatible with LVCMOS levels
* Flow-through architecture for optimum PCB design
* Latch-up performance exceeds 100mA
* ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0)
* Available in 96-pin LFBGA package



Application

* Ideally suited for DDR2 DIMM registered applications
* SSTU32864 is optimized for DDR2 Raw Cards B and C R-DIMMs
* SSTU32864A is optimized for DDR2 Raw Card A R-DIMMs
* Along with CSPU877, zero delay PLL clock buffer, provides
   complete solution for DDR2 DIMMs



Specifications

Symbol
Description
Max.
Unit
VDD Supply Voltage Range
0.5 to 2.5
V

VI(2,3)
Input Voltage Range
0.5 to 2.5
V

VO(2,3)
Output Voltage Range
0.5 to VDD+0.5
V
IIK Input Clamp Current VI < 0
±50
mA
VI > VDD
IOK Output Clamp Current VO < 0
±50
mA
VO > VDD
IO Continuous Output Current,
VO = 0 to VDD
±50
mA
VDD Continuous Current through each
VDD or GND
±100
mA
TSTG Storage Temperature Range
65 to +150
°C



Description

The IDT74SSTU32864A is a 25-bit 1:1 / 14-bit 1:2 configurable registered buffer designed for 1.7V to 1.9V VDD operation.  All clock and data inputs are compatible with the JEDEC standard for SSTL_18.  The control inputs are LVCMOS.  All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load.

The IDT74SSTU32864A operates from a differential clock (CLK and CLK).Data are registered at the crossing of CLK going high and CLK going low.


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