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Part Number: IDT74SSTVF16857
Description: The SSTVF16857 is a 14-bit registered buffer designed for 2.3V-2.7V VDD and supports low standby opera...
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IDT74SSTVF16857
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DataSheet
General Description
IDT74SSTVF16857 General Description
The SSTVF16857 is a 14-bit registered buffer designed for 2.3V-2.7V VDD and supports low standby operation. All data inputs and outputs are SSTL_2 level compatible with JEDEC standard for SSTL_2.
RESETis an LVCMOS input since it must operate predictably during the power-up phase. RESET, which can be operated independent of CLK and CLK, must be held in the low state during power-up in order to ensure predictable outputs (low state) before a stable clock has been applied.
RESET, when in the low state, will disable all input receivers, reset all registers, and force all outputs to a low state, before a stable clock has been applied. With inputs held low and a stable clock applied, outputs will remain low during the Low-to-High transition of RESET.
IDT74SSTVF16857 Maximum Ratings
|
Symbol |
Description |
Max. |
Unit |
|
VDD or VDDQ |
Supply Voltage Range |
0.5 to 3.6 |
V |
|
VI(2) |
Input Voltage Range |
0.5 to VDD +0.5 |
V |
|
VO(3) |
Output Voltage Range |
0.5 to VDDQ +0.5 |
V |
|
IIK |
Input Clamp Current, VI < 0 |
50 |
mA |
|
IOK |
Output Clamp Current, VO < 0 or VO > VDDQ |
±50 |
mA |
|
IO |
Continuous Output Current, VO = 0 to VDDQ |
±50 |
mA |
|
VDD |
Continuous Current through each VDD, VDDQ or GND |
±100 |
mA |
|
TSTG |
Storage Temperature Range |
65 to +150 |
°C |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed.
3. The output current will flow if the following conditions are observed:
a) Output in HIGH state
b) VO = VDDQ
IDT74SSTVF16857 Features
• 2.3V to 2.7V Operation
• SSTL_2 Class I style data inputs/outputs
• Differential CLK input
• RESET control compatible with LVCMOS levels
• Flow-through architecture for optimum PCB design
• Drive up to equivalent of 14 SDRAM loads
• Latch-up performance exceeds 100mA
• ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0)
• Available in TSSOP package
• SSTL_2 Class I style data inputs/outputs
• Differential CLK input
• RESET control compatible with LVCMOS levels
• Flow-through architecture for optimum PCB design
• Drive up to equivalent of 14 SDRAM loads
• Latch-up performance exceeds 100mA
• ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0)
• Available in TSSOP package
IDT74SSTVF16857 Typical Application
• Along with CSPT857C, Zero Delay PLL Clock buffer, provides complete solution for DDR1 DIMMs
IDT74SSTVF16857 Connection Diagram
IDT74SSTVF16857
PDF/DataSheet Download
- Datasheet: IDT74SSTVF16857
- File Size: 55920 KB
- Manufacturer: IDT
- Click here to Download
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