IDTCV123

IDTCV123 is a 56 pin clock device. The CPU output buffer is designed to support up to 400MHz processor. This chip has three PLLs inside for CPU/ SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial ATA clock provides high accuracy frequency.

IDTCV123 also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Static PLL frequency divide error of IDTCV123  can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. Each CPU/SRC/PCI, SATA clock has IDTCV123 own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups.