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IDTCV125

Features: • Power management control suitable for notebook applications• One high precision PLL for CPU, SSC and N programming• One high precision PLL for SRC/PCI, supports 100MHz output frequency, SSC and N programming• One high precision PLL for LVDS. Supports 100/96MHz o...

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SeekIC No. : 004373399 Detail

IDTCV125: Features: • Power management control suitable for notebook applications• One high precision PLL for CPU, SSC and N programming• One high precision PLL for SRC/PCI, supports 100MHz ...

IDTCV125 Data Sheet

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Part Number:
IDTCV125
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/24

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Product Details

Description



Features:

• Power management control suitable for notebook applications
• One high precision PLL for CPU, SSC and N programming
• One high precision PLL for SRC/PCI, supports 100MHz output
   frequency, SSC and N programming
• One high precision PLL for LVDS. Supports 100/96MHz output
   frequency, SSC programming
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Support spread spectrum modulation, 0.5 down spread and others
• Support SMBus block read/write, index read/write
• Selectable output strength for REF
• Allows for CPU frequency to change to a slower frequency to
   conserve power when an application is less executionintensive
• Smooth transition for N programming
• Available in TSSOP package


Pinout

Connection Diagram


Specifications

Symbol Description Min Max UNIT
VDDA 3.3V Core Supply Voltage   4.6 V
VDDIN 3.3V Logic Input Supply Voltage GND - 0.5 4.6 V
TSTG Storage Temperature -65 +150
TAMBIENT Ambient Operating Temperature 0 +70
TCASE Case Temperature   +115
ESD Prot Input ESD Protection
Human Body Model		 2000   V
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.


Description

IDTCV125 is a 56 pin clock device, incorporating both Intel CK410M and CKSSCD requirements, for Intel advance P4 processors. The CPU output buffer is designed to support up to 400MHz processor. This chip of IDTCV125 has four PLLs inside for CPU, SRC/PCI, LVDS, and 48MHz/DOT96 IO clocks. IDTCV125 also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Static PLL frequency divide error can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. Each CPU/SRC/LVDS has IDTCV125 own Spread Spectrum selection.




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