Purchase IDT 79R3081, In-stock IDT 79R3081 From SeekIC.
- Table of contents:
IDT 79R3081
-
Suppliers
DataSheet
General Description
IDT 79R3081 Maximum Ratings
|
Symbol |
Rating |
Commercial |
Military |
Unit |
|
VTERM |
Terminal Voltage with Respect to GND |
0.5 to +7.0 |
0.5 to +7.0 |
V |
|
TC |
Operating Case Temperature |
0 to +85 |
55 to +125 |
°C |
|
TBIAS |
Case Temperature Under Bias |
55 to +125 |
65 to +135 |
°C |
|
TSTG |
Storage Temperature |
55 to +125 |
65 to +155 |
°C |
|
VIN |
Input Voltage |
0.5 to +7.0 |
0.5 to +7.0 |
V |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VIN minimum = 3.0V for pulse width less than 15ns. VIN should not exceed VCC +0.5V.
3. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
IDT 79R3081 Features
• Instruction set compatible with IDT79R3000A, R3041, R3051, and R3071 RISC CPUs
• High level of integration minimizes system cost
- R3000A Compatible CPU
- R3010A Compatible Floating Point Accelerator
- Optional R3000A compatible MMU
- Large Instruction Cache
- Large Data Cache
- Read/Write Buffers
• 43VUPS at 50MHz
- 13MFlops
• Flexible bus interface allows simple, low cost designs
• Optional 1x or 2x clock input
• 20 through 50MHz operation
• "V" version operates at 3.3V
• 50MHz at 1x clock input and 1/2 bus frequency only
• Large on-chip caches with user configurability
- 16kB Instruction Cache, 4kB Data Cache
- Dynamically configurable to 8kB Instruction Cache,8kB Data Cache
- Parity protection over data and tag fields
• Low cost 84-pin packaging
• Superset pin- and software-compatible with R3051, R3071
• Multiplexed bus interface with support for low-cost, lowspeed memory systems with a high-speed CPU
• On-chip 4-deep write buffer eliminates memory write stalls
• On-chip 4-deep read buffer supports burst or simple block reads
• On-chip DMA arbiter
• Hardware-based Cache Coherency Support
• Programmable power reduction mode
• Bus Interface can operate at half-processor frequency
• High level of integration minimizes system cost
- R3000A Compatible CPU
- R3010A Compatible Floating Point Accelerator
- Optional R3000A compatible MMU
- Large Instruction Cache
- Large Data Cache
- Read/Write Buffers
• 43VUPS at 50MHz
- 13MFlops
• Flexible bus interface allows simple, low cost designs
• Optional 1x or 2x clock input
• 20 through 50MHz operation
• "V" version operates at 3.3V
• 50MHz at 1x clock input and 1/2 bus frequency only
• Large on-chip caches with user configurability
- 16kB Instruction Cache, 4kB Data Cache
- Dynamically configurable to 8kB Instruction Cache,8kB Data Cache
- Parity protection over data and tag fields
• Low cost 84-pin packaging
• Superset pin- and software-compatible with R3051, R3071
• Multiplexed bus interface with support for low-cost, lowspeed memory systems with a high-speed CPU
• On-chip 4-deep write buffer eliminates memory write stalls
• On-chip 4-deep read buffer supports burst or simple block reads
• On-chip DMA arbiter
• Hardware-based Cache Coherency Support
• Programmable power reduction mode
• Bus Interface can operate at half-processor frequency
IDT 79R3081 Connection Diagram
IDT 79R3081
PDF/DataSheet Download
- Datasheet: IDT 79R3081
- File Size: 914564 KB
- Manufacturer: IDT
- Click here to Download
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