IS42S16400

The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits.

The 64Mb SDRAM includes an AUTO REFRESH MODE,and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible.

The 64Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access.

A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and rovide seamless, high-speed, random-access operation. DRAM read and write accesses are burst oriented starting t a selected location and continuing for a programmed umber of locations in a programmed sequence. The egistration of an ACTIVE command begins accesses, ollowed by a READ or WRITE command. The ACTIVE ommand in conjunction with address bits registered are sed to select the bank and row to be accessed (BA0, BA1 elect the bank; A0-A11 select the row). The READ or RITE commands in conjunction with address bits registered re used to select the starting column location for he burst access.

Programmable READ or WRITE burst lengths consist of , 2, 4 and 8 locations or full page, with a burst terminate option.