IS45S32200C1

Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. A_ll voltages are referenced to GND.
3. V_IH (max) = V_DDQ + 2.0V with a pulse width 3 ns. The pluse width cannot be greater than one third of the cycle rate.
4. V_IL (min) = GND 2.0V with a pulse < 3 ns. The pluse width cannot be greater than one third of the cycle rate.
5. An initial pause of 100us is required after power up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (Vdd and VddQ must be powered up simultaneously. GND and GNDQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated anytime the tREF refresh requirement is exceeded.

ISSI's 64Mb Synchronous DRAM IS45S32200C1 is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve highspeed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.