IS61C512

Features: • Pin compatible with 128K x 8 devices• High-speed access time: 15, 20, 25, 35 ns• Low active power: 500 mW (typical)• Low standby power- 250 W (typical) CMOS standby• Output Enable (OE) and two Chip Enable(CE1 and CE2) inputs for ease in applications•...

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IS61C512 Picture
SeekIC No. : 004379127 Detail

IS61C512: Features: • Pin compatible with 128K x 8 devices• High-speed access time: 15, 20, 25, 35 ns• Low active power: 500 mW (typical)• Low standby power- 250 W (typical) CMOS stand...

floor Price/Ceiling Price

Part Number:
IS61C512
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/29

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Product Details

Description



Features:

• Pin compatible with 128K x 8 devices
• High-speed access time: 15, 20, 25, 35 ns
• Low active power: 500 mW (typical)
• Low standby power
- 250 W (typical) CMOS standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply



Pinout

  Connection Diagram


Specifications

Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND 0.5 to +7.0 V
TBIAS Temperature Under Bias 10 to +85
TSTG Storage Temperature 65 to +150
PT Power Dissipation 1.5 W
IOUT DC Output Current (LOW) 20 mA

Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.




Description

The ICSI IS61C512 is a very high-speed, low power, 65,536 word by 8-bit CMOS static RAMs. They are fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices.

When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 1 mW (typical) with CMOS input levels.

Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory.

The IS61C512 is available in 32-pin 300mil DIP, SOJ and 8*20mm TSOP-1 packages.




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